The present invention relates to a semiconductor device and a manufacturing technique for the same. Particularly, the present invention is concerned with a semiconductor device having a capacitor element and a technique applicable effectively to the manufacture of the semiconductor device.
In Japanese Unexamined Patent Publication No. 2003-100887 (Patent Literature 1) there is described a technique for improving the reliability of an upper-layer electrode/lower-Layer electrode structure formed with an insulating film therebetween. More particularly, a lower-layer electrode and an upper-layer electrode are stacked in this order on a silicon substrate. In this case, a contact hole for the upper-layer electrode, which hole is for coupling the upper-layer electrode to an overlying wiring layer, is formed in a region positioned above an isolation region which is formed separately from the lower-layer electrode.
In Japanese Unexamined Patent Publication No. 2003-124356 (Patent Literature 2) there is described a technique related to a semiconductor device such as a flash memory having a capacitor element used for example in a charge pump circuit, whereby an increase of chip area is suppressed, the capacitance of the capacitor element can be set highly accurately, and the number of manufacturing steps can be reduced. More particularly, on a field oxide film there is formed a lower electrode of the capacitor element under self-aligning with a trench portion. By so doing, according to Patent Literature 2, the lower electrode and a floating gate electrode in a memory cell portion can be formed simultaneously in the same process. The lower electrode is enclosed with a trench portion formed in a field oxide film. An upper electrode formed in the same process as a control gate electrode is formed on the lower electrode through an insulating film formed in the same process as a gate-to-gate insulating film in the memory cell portion. In this technique, the upper electrode is extended to the exterior of the lower electrode and in this extended region there is formed a plug coupled to the upper electrode.
In Japanese Unexamined Patent Publication No. 2002-313932 (Patent Literature 3) there is described, in connection with a semiconductor device having a capacitor element, a technique for preventing the occurrence of short-circuit caused by silicide and leak current in side wall portions formed on side portions of a capacitor electrode. More particularly, a lower capacitor electrode, a capacitor insulating film and an upper capacitor electrode are formed on an element isolation region of a silicon substrate. Thereafter, a silicon oxide film is formed on the whole of an upper surface of the silicon substrate. Onto this silicon oxide film is then formed a resist pattern which covers from a certain range inside an edge portion of the upper capacitor electrode up to a certain range outside the edge portion. Then, anisotropic etching is performed to form side walls which cover side faces of the lower capacitor electrode and side walls which cover side faces and an edge portion of an upper surface of the upper capacitor electrode. Thereafter, a metal silicide film is formed on surfaces of the upper and lower capacitor electrodes not covered with the side walls.